For clocking memory devices, phase lock loops (PLLS) are usually employed which receive a reference clock signal generated by the clock and generate therefrom a control clock signal phase-locked thereto for controlling the memory. For noise immunity both the reference clock signal and the control clock signal are each provided as a differential clock signal pair. Since the phase-frequency detector usually contained in the PLL requires single-ended signals for implementing the phase comparison, both the reference clock signal pair generated by the reference clock and the control clock signal pair output by the PLL need to be converted into a single-ended signal. One example of such a circuit assembly in which this signal conversion is made use of in conjunction with a PLL is to be found in the Texas Instruments type CDCV857A integrated circuit, a data sheet of which was publicized in April 2001. On page 2 of this data sheet both the reference clock signal pair and the feedback control clock signal pair have a separate circuit assembly for converting these differential clock signal pairs into single-ended signals.
For proper functioning of the PLL, the shift in phase between the control clock signal pair output thereby and the reference clock signal pair supplied to it by the reference clock is of salient importance since it is from this phase difference that the error signal is generated with the aid of which phase locking is implemented. It is thus a mandatory requirement that the circuit assemblies used for converting each signal pair into single-ended signals must not produce any phase shift which falsifies the existing phase shift between the feedback control clock signal pair and the reference clock signal pair generated by the reference clock. In other words, there must be no skew in the circuit assemblies. Since, however, the signals to be converted in each case originate from different sources, the voltages at points at which the edges of each differential clock signal pair cross jitter. It is due to this jitter that skew materializes in conversion, resulting in the phase relationship of the signals to be compared in the phase-frequency detector being falsified in thus no longer ensuring phase locking to the frequency of the reference clock signal pair. Clocking advanced memory devices necessitates, however, a highly accurate phase and frequency control, since even a picosecond skew may already cause a false response of such memory devices.